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PCIe

Table of Contents

PCIe Topology

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Link and Lane

Figure 1. PCIe link

A lane represents a set of differential signal pairs (one pair for transmission, one pair for reception). The data rates supported by each lane are listed in Table 1.

Table 1. PCIe Signaling Characteristics

Data Rate Modulation Encoding Effective Data Rate (Per-Lane) Base Specification Revision
6.x 5.x 4.x 3.0 2.0 1.0
2.5 GT/s NRZ 8b/10b 2 Gbit/s ✔ ✔ ✔ ✔ ✔ ✔
5.0 GT/s NRZ 8b/10b 4 Gbit/s ✔ ✔ ✔ ✔ ✔
8.0 GT/s NRZ 128b/130b ~8 Gbit/s ✔ ✔ ✔ ✔
16.0 GT/s NRZ 128b/130b ~16 Gbit/s ✔ ✔ ✔
32.0 GT/s NRZ 128b/130b ~32 Gbit/s ✔ ✔
64.0 GT/s PAM4 1b/1b 64 Gbit/s ✔

As shown in Figure 1, a link can support multiple lanes (The number of lanes supported by each revision is listed in Table 2). So the data rate of a link is calculated by: $$LinkRate = LaneRate * LaneNumber$$

Table 2. The number of lanes supported by each revision

Revision x1 x2 x4 x8 x16
6.0 ✔ ✔ ✔ ✔ ✔

Fabric Topology

mindmap ))PCie Components(( RC Endpoints Legacy PCIe RCiEP Switch RCEC PCIe to PCI/PCI-X Bridge

PCIe Layer

Transaction Layer

The transaction layer is responsible for:

  • assembling and disassembling the TLP..
  • managing credit-based flow control.

It supports four address spaces:

  • Memory Space
  • I/O Space
  • Configuration Space
  • Message Space

Data Link Layer

The data link layer is responsible for:

  • link management
  • data integrity

Physical Layer

The physical layer includes all circuitry for interface operation, including:

  • driver and input buffers
  • parallel-to-serial and serial-to-parallel conversion
  • PLL(s)
  • impedance matching circuitry

1.5.4 Layer Functions and Services

Notes

References

Further Reading

  • PCI Express® Base Specification Revision 6.0
Creation Date: 2023/12/04, Last modified: 2023/12/07, Author: Siyuan Liu

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