RISC-V

RISC-V ISA

All content on this page is from RISC-V Spec.
ISA Description
RV32I Provide 32-bit address spaces.
RV64I Provide 64-bit address spaces.
RV32E A variant of the RV32I base instruction set, which has half the number of integer registers.
RV128I Provide a flat 128-bit address space.

Each base integer ISA can be extended with one or more optional instruction-set extensions, and RISC-V foundation divides each RISC-V instruction-set encoding space (and related encoding spaces such as the CSRs) into three disjoint categories:

  • Standard
    Standard encodings are defined by the Foundation, and shall not conflict with other standard extensions for the same base ISA. See Table 1 for supported standard extensions.
  • Reserved
    Reserved encodings are currently not defined but are saved for future standard extensions.
  • Custom
    Custom encodings shall never be used for standard extensions and are made available for vendor-specific non-standard extensions.

Table 1. Standard Extensions

Symbol Name Description
I Base integer ISA Contains integer computational instructions, integer loads, integer stores, and control-
flow instructions.
M Integer multiplication and division extension Adds instructions to multiply and divide values held in the integer registers
A Atomic instruction extension Adds instructions that atomically read, modify, and write memory for inter-processor synchronization.
F Single-precision floating-point extension Aadds floating-point registers, single-precision computational instructions, and single-precision loads and stores.
D Double-precision floating-point extension Expands the floating-point registers, and adds double-precision computational instructions, loads, and stores.
C Compressed instruction extension Provides narrower 16-bit forms of common instructions
  • IALIGN
    The instruction-address alignment constraint the implementation enforces.
  • ILEN
    The maximum instruction length supported by an implementation, and which is always a multiple of IALIGN.

Table 2. Instruction-length encoding convention

Length(bit) Convention
16 bits [1:0] equal to 00, 01, or 10.
32 bits [1:0] equal to 11.
48 bits [5:0] equal to 011111.
64 bits [6:0] equal to 0111111.
[80, 176] - bits [14:12] giving the number of 16-bit words in addition to the first 5×16-bit words.
- bits[6:0] equal to 1111111.
>= 192 (Reserved) bits [14:12] equal to 111', bits [6:0] equal to 1111111''.

Figure 1. RISC-V instruction length encoding

Only the 16-bit and 32-bit encodings are considered frozen at this time(1).

(1) Dec 13 2019
  • "The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 20191213", Editors Andrew Waterman and Krste Asanović, RISC-V Foundation, December 2019
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