Table of Contents
A64 Instruction
Document ARM instructions I have used.
mindmap
A64
Branch
Exception generation
System instruction
Cache maintenance
IC - Instruction Cache
DC - Data Cache
Loads and stores
Data processing < immediate >
Data processing < register >
Qucik Search Table
| Instruction | Ext | Feature | Description |
|---|---|---|---|
| STP | Store Pair of Registers | Calculates an address from a base register value and an immediate offset, and stores two 32-bit words or two 64-bit doublewords to the calculated address, from two registers | |
| LDADD | Atomic add | LSE | |
| LDCLR | Atomic add on byte | LSE | |
| LDEOR | Atomic exclusive OR | LSE | |
| LDSET | Atomic bit set | LSE | |
| LDMAX | Atomic signed maximum | LSE | |
| LDMIN | Atomic signed minimum | LSE | |
| LDUMAX | Atomic unsigned maximum | LSE | |
| LDUMIN | Atomic unsigned minimum | LSE | |
| STADD | Atomic add, without return | LSE | |
| STCLR | Atomic bit clear, without return | LSE | |
| STEOR | Atomic exclusive OR, without return | LSE | |
| STSET | Atomic bit set, without return | LSE | |
| STMAX | Atomic signed maximum, without return | LSE | |
| STMIN | Atomic signed minimum, without return | LSE | |
| STUMAX | Atomic unsigned maximum, without return | LSE | |
| STUMIN | Atomic unsigned minimum, without return | LSE |