SD Host Controller
- Features List
  - Auto CMD23
- Further Reading

SD Host Controller

Introduce the SD host controller (SDHC) specified in SD specification.

SDHC is the standard controller specified by SD Association to manage SD Cards (SD Memory and SDIO).

SDHC has been extended in connection with the Physical Layer functions extension. Major improvement aimed increase of data transfer rate by supporting higher SD bus speed modes and improvement of Direct Memory Access (DMA).

SD Host Ver.2 supported ADMA2 that can handle scattered paging data in system memory (scatter gather DMA).
SD Host Ver.3 supported UHS-I bus modes.
SD Host Ver.4 supported UHS-II bus modes, ADMA3 ⁽¹⁾ and 64-bit system memory addressing.

Features List

Feature		Version
Description	Key Component	2.00	3.00	4.00	4.10	4.20
ADMA2 16-bit Data Length	ADMA2 descriptor	-
ADMA2 26-bit Data Length	ADMA2 descriptor	-	-	-
Re-define SDMA_R to 32-bit Block Count	SDMA_R `000h`	-	-	-
PLL control	Clock Control `02Ch`	-	-	-
10-bit divided clock mode	Clock Control `02Ch`	-
Programmable clock mode	Clock Control `02Ch`	-
Clock generator select (Programmable clock mode / Divided clock mode)	Clock Control `02Ch`	-		-	-	-
Auto CMD12	Transfer Mode `00Ch`
Auto CMD23	Transfer Mode `00Ch`	-
Auto CMD auto select	Transfer Mode `00Ch`	-	-	-
Response error check	Transfer Mode `00Ch [8:6]`	-	-

Auto CMD23

32-bit block count value for CMD23 is set to SDMA. ^[a]

Notes

⁽¹⁾ ADMA3 can execute multiple of ADMA2 data transfers without intervention of Host Driver by Descriptor programing.

References

^[a] SD Host Controller Simplified Specification. SD Association, Jul 2018, pp.43.

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