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====== PCIe Topology ======

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===== Link and Lane  =====

<wrap #pcie-link />
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<WRAP nof>Figure 1. PCIe link</WRAP>

A lane represents a set of __differential signal pairs__ (one pair for transmission,
one pair for reception). The data rates supported by each lane are listed in
[[#lane-data-rate|Table 1]]. 

<WRAP not><wrap #lane-data-rate />Table 1. PCIe Signaling Characteristics</WRAP>
^  Data Rate  ^  Modulation  ^  Encoding  ^  Effective Data Rate (Per-Lane)  ^  Base Specification Revision                                ||||||
| :::         | :::          | :::        | :::                   ^ 6.x                           ^ 5.x  ^ 4.x  ^ 3.0  ^ 2.0  ^ 1.0  ^
| 2.5 GT/s    | NRZ          | 8b/10b     | 2 Gbit/s              | ✔                             | ✔    | ✔    | ✔    | ✔    | ✔    |
| 5.0 GT/s    | NRZ          | 8b/10b     | 4 Gbit/s              | ✔                             | ✔    | ✔    | ✔    | ✔    |      |
| 8.0 GT/s    | NRZ          | 128b/130b  | ~8 Gbit/s             | ✔                             | ✔    | ✔    | ✔    |      |      |
| 16.0 GT/s   | NRZ          | 128b/130b  | ~16 Gbit/s            | ✔                             | ✔    | ✔    |      |      |      |
| 32.0 GT/s   | NRZ          | 128b/130b  | ~32 Gbit/s            | ✔                             | ✔    |      |      |      |      |
| 64.0 GT/s   | PAM4         | 1b/1b      | 64 Gbit/s             | ✔                             |      |      |      |      |      |

As shown in [[#pcie-link|Figure 1]], a link can support multiple lanes
(The number of lanes supported by each revision is listed in [[#lane-number-tab|Table 2]]).
So the data rate of a link is calculated by:
$$LinkRate = LaneRate * LaneNumber$$

<WRAP not><wrap #lane-number-tab />Table 2. The number of lanes supported by each revision</WRAP>
^ Revision  ^ x1  ^ x2  ^ x4  ^ x8  ^ x16  ^
| 6.0       | ✔   | ✔   | ✔   | ✔   | ✔    |

===== Fabric Topology =====

{{:network:pcie:start:media:20231204-225403.png?direct&600}}

<mermaid>
mindmap
))PCie Components((
  RC
  Endpoints
    Legacy
    PCIe
    RCiEP
  Switch
  RCEC
  PCIe to PCI/PCI-X Bridge
</mermaid>

===== PCIe Layer =====

{{ :network:pcie:start:media:pcie-layer.svg |}}

==== Transaction Layer ====

The <wrap element>transaction layer</wrap> is responsible for:
  * assembling and disassembling the <wrap abbr>TLP</wrap>..
  * managing credit-based flow control.

It supports four address spaces:
  * Memory Space
  * I/O Space
  * Configuration Space
  * Message Space

==== Data Link Layer ====

The <wrap element>data link layer</wrap> is responsible for:
  * link management
  * data integrity

==== Physical Layer ====

The <wrap element>physical layer</wrap> includes all circuitry for interface operation, including:
  * driver and input buffers
  * parallel-to-serial and serial-to-parallel conversion
  * PLL(s)
  * impedance matching circuitry

<WRAP round todo 60%>
1.5.4 Layer Functions and Services
</WRAP>


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===== Further Reading =====

  * <wrap doc>PCI Express® Base Specification Revision 6.0</wrap>