~~PAGEIMAGE:arch:risc-v:sipeed:rv-dock-write-perf:20240904-231454.png~~

====== RV-Dock C906 Write Performance ======

{{template>meta:template:pageinfo#tpl|desc=This page documents some experiment data on **XuanTie C906** cache write performance. }}

According to the **D1** user manual, the integrated **C906** supports __32kB D-cache__ and the following __write-through thresholds__:
  * continuously storing ''4'' full cache lines.
  * continuously storing ''16'' full cache lines.
  * continuously storing ''64'' full cache lines.
Therefore, I would like to investigate the write performance under different configurations.

==== Environment And Benchmark ====

=== Environment ===

  * Lichee RV-Dock board.
  * Memory test region [''0x30000'', ''0x44000'').

=== Benchmark ===

  - Specify ''1K'' region $R$ [$A_1$, $A_2$].
  - <wrap #step-2 />Repeat writing data continuously from $A_1$ to $A_2$ until ''128MB'' of data is written. Then get the consumed time as a sample point.
  - Increase $A_2$ by ''1kB'' and jump to [[#step-2|step 2]].

==== Experiment Result ====

<WRAP group>
<WRAP column half>
=== Disable D-Cache ===

{{:arch:risc-v:sipeed:rv-dock-write-perf:20240904-230750.png?600}}

=== Enable D-Cache And Disable Write-Through ===

{{:arch:risc-v:sipeed:rv-dock-write-perf:20240904-231352.png?600}}
</WRAP>

<WRAP column half>
=== Enable D-Cache And Enable Write-Through With 4 Cache Line ===

{{:arch:risc-v:sipeed:rv-dock-write-perf:20240904-231206.png?600}}

=== Enable D-Cache And Enable Write-Through With 16 Cache Line ===

{{:arch:risc-v:sipeed:rv-dock-write-perf:20240904-231230.png?600}}

=== Enable D-Cache And Enable Write-Through With 64 Cache Line ===

{{:arch:risc-v:sipeed:rv-dock-write-perf:20240904-231258.png?600}}
</WRAP>
</WRAP>

=== All In One ===

{{:arch:risc-v:sipeed:rv-dock-write-perf:20240904-231454.png?600}}