~~PAGEIMAGE:arch:risc-v:riscv.svg~~
{{htmlmetatags>metatag-robots=(noindex,nofollow)}}

====== RISC-V ISA ======

{{template>meta:template:pageinfo#tpl|desc=All content on this page is from RISC-V Spec.}}

===== Base ISA =====

<datatables>
^ ISA     ^ Description                                                                                   ^
| RV32I   | Provide 32-bit address spaces.                                                                |
| RV64I   | Provide 64-bit address spaces.                                                                |
| RV32E   | A variant of the RV32I base instruction set, which has half the number of integer registers.  |
| RV128I  | Provide a flat 128-bit address space.                                                         |
</datatables>

===== Optional Instruction-Set Extensions =====

__Each base integer ISA can be extended with one or more optional instruction-set extensions__,
and RISC-V foundation divides each RISC-V instruction-set encoding space (and related encoding
spaces such as the CSRs) into three disjoint categories: 

  * **Standard** \\
    Standard encodings are defined by the Foundation, and shall not conflict with other standard 
    extensions for the same base ISA. See [[#standard-extension|Table 1]] for supported standard extensions.
  * **Reserved** \\
     Reserved encodings are currently not defined but are saved for future standard extensions.
  * **Custom** \\
    Custom encodings shall never be used for standard extensions and are made available for 
    vendor-specific non-standard extensions.

<WRAP not><wrap #standard-extension />Table 1. Standard Extensions</WRAP>
<datatables>
^ Symbol  ^ Name                                           ^ Description                                                                                                          ^
| ''I''   | Base integer ISA                               | Contains integer computational instructions, integer loads, integer stores, and control-\\ flow instructions.        |
| ''M''   | Integer multiplication and division extension  | Adds instructions to multiply and divide values held in the integer registers                                        |
| ''A''   | Atomic instruction extension                   | Adds instructions that atomically read, modify, and write memory for inter-processor synchronization.                |
| ''F''   | Single-precision floating-point extension      | Aadds floating-point registers, single-precision computational instructions, and single-precision loads and stores.  |
| ''D''   | Double-precision floating-point extension      | Expands the floating-point registers, and adds double-precision computational instructions, loads, and stores.       |
| ''C''   | Compressed instruction extension               | Provides narrower 16-bit forms of common instructions                                                                |
</datatables>

===== Base Instruction-Length Encoding =====

  * ''IALIGN'' \\
    The instruction-address alignment constraint the implementation enforces.
  * ''ILEN'' \\
    The maximum instruction length supported by an implementation, and which is always a multiple of ''IALIGN''.
    
<WRAP not>Table 2. Instruction-length encoding convention</WRAP>
^ Length(bit)        ^ Convention                                                                                                                            ^
| 16                 | bits [1:0] equal to ''00'', ''01'', or ''10''.                                                                                        |
| 32                 | bits [1:0] equal to ''11''.                                                                                                           |
| 48                 | bits [5:0] equal to ''011111''.                                                                                                       |
| 64                 | bits [6:0] equal to ''0111111''.                                                                                                      |
| [80, 176]          | - bits [14:12] giving the number of __16-bit words__ in addition to the first 5×16-bit words. \\   - bits[6:0] equal to ''1111111''.  |
| >= 192 (Reserved)  | bits [14:12] equal to ''111', bits [6:0] equal to ''1111111''.                                                                        |    

{{:arch:risc-v:isa:20240304-220756.png}}
<WRAP nof>Figure 1. RISC-V instruction length encoding</WRAP>

<callout type="warning">
Only the **16-bit** and **32-bit** encodings are considered frozen at this time((note:>Dec 13 2019)).
</callout>

===== Assembler Mnemonics =====

{{:arch:risc-v:isa:20240322-003312.png?600}}

{{template>meta:template:refnote#note}}

===== Further Reading =====

  * "The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 20191213",
    Editors Andrew Waterman and Krste Asanović, RISC-V Foundation, December 2019