~~PAGEIMAGE:arch:arm:a:media:img:global-monitor.svg~~

====== ARMv8 Synchronization Model ======

{{template>meta:template:pageinfo#tpl
|desc=Introduce the elements and exclusive states in the ''ARMv8'' synchronization model.}}

ARMv8 designs a synchronization model to provide non-blocking synchronization.
This model includes the following key elements:
  * <wrap isa>Load-Exclusive</wrap> / <wrap isa>Store-Exclusive</wrap> 
    instruction pair and <wrap isa>Clear-Exclusive</wrap> instruction.
  * Memory block accessed by the above instruction pair.
  * Local exclusive monitor, or local monitor, for non-shareable and shareable memory
    ((note:>Todo: Introduce shareable and non-shareable.)).
  * Global exclusive monitor, or global monitor, for shareable memory.

ARMv8 defines two states for memory blocks accessed by PE:
  * <wrap state>Exclusive Access</wrap> state.
  * <wrap state>Open Access</wrap> state.

===== Access States =====

==== Exclusive Access State ====

When a memory block is marked as <wrap state>Exclusive Access</wrap> for a PE, 
this means that this PE can modify the data of that memory block by issuing a
<wrap isa>Store-Exclusive</wrap> instruction.

==== Open Access State ====

When a memory block is marked as <wrap state>Open Access</wrap> for a PE, this
means that this PE cannot modify the data of that memory block by issuing a
<wrap isa>Store-Exclusive</wrap> instruction.

==== State Machine ====

ARMv8 gives different state machine diagrams for [[#Local Monitor|local monitor]]
and [[#Global Monitor|global monitor]]. I cut these figures directly from Spec
because I thought it was clear enough to understand.

<callout type="info">
Before looking at the figures, let me give some advice.
  * It is important to note that the ''Marked_address'' in the figures is a memory
    block. You can figure it out by reading 
    [[#Exclusives Reservation Granule|Exclusives Reservation Granule]].
  * The operations with ''*'' at the end are IMPLEMENTATION DEFINED, so I don't think
    it's necessary to focus more on them, unless you want to design an ARMv8 based CPU.
</callout>

<callout>
The below figure shows the state machine for the local monitor and the effect of each
of the operations shown in the figure.
\\ \\
{{:arch:arm:a:media:img:20230520-163716.png?600&direct}}
</callout>

<callout>
The below figure shows the state machine for PE(n) in a global monitor.
\\ \\
{{:arch:arm:a:media:img:20230520-164158.png?600&direct}}
</callout>

<callout type="info">
An exception return clears the local monitor((:arm-ddi0487-i-a-c2-9-4)).
That means that the marked state of all memory blocks monitored by the local monitor will 
be set to <wrap state>Open Access</wrap> state (or another unspecified state, which must 
not be <wrap state>Exclusive Access</wrap> state).
</callout>

===== Key Elements =====
This section introduces some of the key elements in the synchronization model.
==== Synchronization Primitives ====

There are three types of synchronization primitives:
  * **<wrap isa>Load-Exclusive</wrap>** \\
    When PE executes such an instruction, the data in the specified memory will
    be read out and the memory will be set to or held in <wrap state>Exclusive 
    Access</wrap> state for the observer((note:>I researched the ARMv8 Spec and
I think ''observer'' represents PE. The PE observes the state of the memory
block marked by the monitor.)).

  * **<wrap isa>Store-Exclusive</wrap>** \\
    The result of the execution of such an instruction is determined by the state
    of the memory specified by the address parameter, which is marked by the monitor. 
    * If memory is marked as the <wrap state>Exclusive Access</wrap> state, the store
      takes place and a status value of ''0'' is returned to a register.
    * If memory is marked as the <wrap state>Open Access</wrap> state, no store takes
      place and a status value of ''1'' is returned to a register.

<callout type="info">
When a <wrap isa>Store-Exclusive</wrap> instruction is issued, ARMv8
will check the status of the monitor and whether the memory is marked by the monitor to
determine the execution result. ((:arm-ddi0487-i-a-b2-9-1))((:arm-ddi0487-i-a-b2-9-2))
SO PLEASE NOTE THAT I am just summarizing this state in
one statement. That is, <WRAP>
  * **//The <wrap state>Exclusive Access</wrap> state of memory//** means that the
    monitor is in the <wrap state>Exclusive Access</wrap> state and the memory is marked.
  * **//The <wrap state>Open Access</wrap> state of memory//** means that the monitor
    is in <wrap state>Open Access</wrap> state, or the memory is not marked.
</WRAP>
</callout>

  * **Clear-Exclusive** \\ Such a instruction will clear the 
    <wrap state>Exclusive Access</wrap> state of monitor, which means move to the
    <wrap state>Open Access</wrap> state.

<callout type="info">

The following table lists the synchronization primitives. \\ \\

^ Transaction Size  ^ Additional Semantics        ^ Load-Exclusive           ^ Store-Exclusive           ^ Others                  ^
| Byte              | -                           | <wrap isa>LDXRB</wrap>   | <wrap isa>STXRB</wrap>    | -                       |
| :::               | Load-Acquire/Store-Release  | <wrap isa>LDAXRB</wrap>  | <wrap isa>STLXRB</wrap>   | -                       |
| Halfword          | -                           | <wrap isa>LDXRH</wrap>   | <wrap isa>STXRH</wrap>    | -                       |
| :::               | Load-Acquire/Store-Release  | <wrap isa>LDAXRH</wrap>  | <wrap isa>STLXRRH</wrap>  | -                       |
| Register          | -                           | <wrap isa>LDXR</wrap>    | <wrap isa>STXR</wrap>     | -                       |
| :::               | Load-Acquire/Store-Release  | <wrap isa>LDAXR</wrap>   | <wrap isa>STLXR</wrap>    | -                       |
| Pair              | -                           | <wrap isa>LDXP</wrap>    | <wrap isa>STXP</wrap>     | -                       |
| :::               | Load-Acquire/Store-Release  | <wrap isa>LDAXP</wrap>   | <wrap isa>STLXP</wrap>    | -                       |
| None              | Clear-Exclusive             | -                        | -                         | <wrap isa>CLREX</wrap>  |

Except for the row showing the <wrap isa>CLREX</wrap> instruction, the two
instructions in a single row are a <wrap isa>Load-Exclusive</wrap>/
<wrap isa>Store-Exclusive</wrap> instruction pair.

</callout>

==== Memory ====

=== Memory Type ===

The are two types of memory:
  * ''Non-Shareable'' memory \\ For this type of memory, exclusive access to
    it requires only local monitor.
  * ''Shareable'' memory \\ Exclusive access to this type of memory requires
    both local monitor and global monitor.

=== Exclusives Reservation Granule ===

When the PE executes the <wrap isa>Load-Exclusive</wrap> instruction to load
64-bit data from address A1, the memory block that includes A1 will be marked
for <wrap state>Exclusive Access</wrap>. The size of this memory block is aligned
by <wrap element>exclusives reservation granule</wrap> specified in the ARMv8 Spec.
<wrap element>Exclusives reservation granule</wrap> is IMPLEMENTATION DEFINED in
the range ''4''-''512'' words. And in some implements it can be read from
<wrap reg>CTR</wrap> register, e.g. <wrap reg>CTR_EL0</wrap>.

<callout>
For example, assume that <wrap element>exclusives reservation granule</wrap> is
8 words. When the PE executes the <wrap isa>Load-Exclusive</wrap> instruction to
''0x30'' as shown below, the memory block ''[0x20, 0x3F]'' will be marked as
<wrap state>Exclusive Access</wrap> state.

{{:arch:arm:a:media:img:monitered-memory.svg}}
</callout>

==== Local Monitor ====

The local monitor is located in the PE. It is designed to monitor the
exclusive status of a memory block((note:>I researched the ARMv8 Spec and
it seems to support monitoring only one memory block.)). No PE can
**directly** change the exclusive state of memory blocks monitored by other PEs.

==== Global Monitor ====

The global monitor can either reside within the PE, or exist as a secondary
monitor at the memory interfaces. It is designed to synchronize between
multiprocessor system. The global monitors monitor one memory block for each
PE separately, as shown below.

<callout type="info">
The memories ''M-A'' and ''M-B'' monitored by the global monitor in the
following figure may or may not be the same. If they are identical, either
PE is affected by the store operations issued by the other PE on the common
memory block. This is the key to achieve **synchronization**.
</callout>

{{:arch:arm:a:media:img:global-monitor.svg}}

===== CPU Implementation List =====
<datatables>
^  Table-1. Local monitor in CPU                                                                                                                                                                                                                                                                                                                                   |||
^ CPU                             ^ Location                                                                                                                                                                                                                                                                                       ^ Exclusives Reservation Granule  ^
| A72                             | L1 memory system((:arm-a72-6-4-5))               | 64 bytes, one cache line.       |
| A78AE                           | L1 memory system((:arm-a78ae-6-4-2))  | 64 bytes, one cache line.       |
</datatable>

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===== Further Reading =====

  * [[https://developer.arm.com/documentation/ddi0487/ia/|Arm® Architecture Reference Manual for A-profile architecture]]
    * <wrap clause>B2.9. Exclusive access instructions and Shareable memory locations</wrap>
  * //[[https://patchwork.kernel.org/project/linux-arm-kernel/patch/1472726820-32959-1-git-send-email-vladimir.murzin@arm.com/]]//
  * //[[https://github.com/ARM-software/arm-trusted-firmware/blob/master/lib/locks/exclusive/aarch64/spinlock.S]]//
  * //ARM community//
    * //[[https://community.arm.com/support-forums/f/architectures-and-processors-forum/51294/ldrex-strex-breaked-by-third-task]]//
    * //[[https://community.arm.com/support-forums/f/architectures-and-processors-forum/10361/ldrex-strex-on-the-m3-m4-m7/33045#33045]]//
    * //[[https://community.arm.com/support-forums/f/architectures-and-processors-forum/4273/how-to-understand-armv8-sevl-instruction-in-spin-lock]]//